This invention relates, in general, to phase lock loop testing, and more particularly to a built in self test for a phase lock loop.
It is well known by those skilled in the art that phase lock loop circuits provide a signal of a predetermined frequency. The speed and accuracy of currently manufactured phase lock loops has advanced to the point where outboard testing of a phase lock loop (PLL) may not be possible or cost effective. Testing of a PLL typically involves a functional test (determining whether the PLL locks to a frequency), the frequency range of the PLL, and the accuracy of the frequency generated by the PLL.
Many phase lock loops are programmable for a range of output frequencies. A reference frequency is input to the PLL and the PLL is programmed to generate a specific output frequency. The stability and accuracy of the reference frequency directly impacts the performance characteristics of the PLL. For example, a programmable PLL having a frequency range of 20-120 megahertz (MHz) might use a reference frequency of 15 MHz. Generally, testing requires knowledge of the programmable relationship between the reference frequency and the PLL output frequency, an accurate measurement of the reference frequency, and an accurate measurement of the PLL output frequency. The use of automated external test equipment to measure frequencies in excess of 100 MHz is difficult. External test requires inputs and outputs of the PLL to be brought to pins that can be coupled to the tester, thereby reducing the number of pins available and also increasing parasitic loading on the PLL. Furthermore, some PLL's are embedded within a semiconductor chip and not accessible to a tester. It would be of great benefit if a method for testing a PLL could be provided which eliminates the need for external testing, uses minimal circuitry, and provides accurate characterization of the PLL.